A Reliable High-speed Compact In-memory Matching Circuit for CAM-Application Based on NV-RAM
Abstract
This paper presents an effective approach for
implementing content address memory (CAM) based on Nonvolatile random-access memory (NV-RAM) technologies. We
used the 2T-2R bitcell structure implemented on a 65nm
CMOS process with a special in-memory matching circuit
for realizing low-delay and energy-efficient lookup operations.
The simulation results on Synopsys HSPICE indicate that the
proposed CAM design can achieve a search error rate of
0.03-4.61%, search energy per bit of 4.36-6.47 fJ, and an
extremely small search latency varying from 0.11-0.12 ns
depending on the specific design configurations.
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